GATE CSE · Computer Science and Information Technology
Machine instructions; ALU and control unit; pipelining; memory hierarchy; I/O.
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Q1 · Computer Organization and Architecture · HARD
A CPU has a cache memory with an access time of 2 ns and a main memory with an access time of 50 ns. If the hit ratio is 0.85, what is the effective memory access time (in ns)?
Q2 · Computer Organization and Architecture · HARD
A processor has a cache with an access time of 2 ns and a main memory with an access time of 80 ns. The cache hit ratio is 0.92. What is the effective memory access time (in ns)?
Q3 · Computer Organization and Architecture · HARD
A processor has a 5-stage pipeline with stage delays of 150 ns, 120 ns, 180 ns, 140 ns, and 110 ns. If the pipeline register delay is 10 ns, what is the maximum speedup achievable compared to a non-pipelined implementation executing 100 instructions?
Q4 · Computer Organization and Architecture · MEDIUM
A processor uses a 5-stage instruction pipeline with stages: Fetch (F), Decode (D), Execute (E), Memory (M), and Write-back (W). Each stage takes exactly one clock cycle. Consider executing 8 independent instructions. If the pipeline operates without any hazards or stalls, how many clock cycles are required to complete the execution of all 8 instructions?
Q5 · Computer Organization and Architecture · HARD
A cache memory has an access time of 10 ns and main memory has an access time of 100 ns. If the cache hit ratio is 0.9, what is the effective memory access time (in ns)?